[partial-reconfig] ESM : Platform for Reconfigurable Computing

[Guillaume FORTAINE <gui.fortaine@xxxxxxxxx>]

http://www12.informatik.uni-erlangen.de/research/esm/index.php?flash=no

Despite the announcement made by several companies in the last couple of 
years about the design and production of new and mostly coarse grained 
reconfigurable chips, today's reconfigurable computing platforms are 
still FPGA-based. The growing capacities provided by FPGA as well as 
their partial reconfiguration capabilities have made them one of the 
ultimate reconfigurable device.

Xilinx FPGAs, one of the few partially reconfigurable devices offer 
enough logic to efficiently implement resource demanding applications 
which arise in video, audio and signal processing as well as in other 
fields like mechanical control. Partial reconfiguration is useful to 
increase the flexibility in computation and time-sharing of device 
space. It requires run-time loadable modules to be compiled and stored 
as bitstreams which will then be used to reconfigure the device, i.e. 
allocating space for the computation of the module on the device. The 
development process of modules for todays FPGAs is very tedious and the 
relocation even more difficult and not automated.

For example a module placed at a given location on the device is 
implicitly assigned all the resources in that area. This includes the 
pins, the clock managers and other hard macros like multipliers and 
BlockRAM. As illustrated in Figure 1, each module using resources 
outside its placement area must go through other modules in which area 
the needed resource are located. This situation has three negative 
consequences:

        1.

           Module development: Automatizing the development of modules 
for partial reconfiguration is difficult.
        2.

           Intermodule communication: Placed modules must be able to 
communicate with other modules independent of their placement position.
        3.

           I/O pin constraints: Modules accessing I/O pins are not 
relocatable, because each pin has a fixed physical location.



Figure 1: Problems of existing FPGA boards when used for partial 
reconfiguration

Up to now, no FPGA platform on the market provides solutions to the 
above problems. Many systems on the market offer various interface for 
audio and video capturing and rendering, for communication and so forth. 
However, each interface is connected to the FPGA using dedicated pins in 
a fixed location. Modules willing to access a given interface like the 
VGA must be placed in the area of the chip where the FPGA signals are 
connected. A relocation is therefore not possible. The purpose of the 
Erlangen Slot Machine is to overcome the deficiencies of existing FPGA 
platforms by providing:

        1.

           Maximal reconfigurability: A revolutionary architecture 
allowing fully partially reconfigurable module relocation, organized in 
slots of variable width.
        2.

           Module development support: Together with the architecture 
a) a firmware layer is provided for supporting module instantiation, 
movement, read back, etc., and b) a tool called SlotComposer may be used to.

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