Re: [partial-reconfig] Spartan-3/3E partial reconfiguration

[Guillaume FORTAINE <gui.fortaine@xxxxxxxxx>]

Hi everybody,

http://www.xilinx.com/support/prealounge/protected/index.htm


 Partial Reconfiguration Early Access software tools

This lounge supports a new Partial Reconfiguration software flow which 
is an extension of the solution described in XAPP 290 
<http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf> (PDF). An overview 
of the new Partial Reconfiguration tools is in the User's Guide. Please 
read the Installation Guide before installing the Software Downloads.

Technical Support is available through your local FAE. If you are 
affiliated with a university, support is available through this e-mail 
address: univ_ea_pr_support@xxxxxxxxxx 
<mailto:univ_ea_pr_support@xxxxxxxxxx>


     Software Downloads

   * Implementation Tools
     <http://www.xilinx.com/support/prealounge/protected/designs/PartialFlow_82i_2.zip>
     (ZIP)
     Modified map, par and library files for partial reconfiguration.
     These software tools only support the Virtex™-4, Virtex-II and
     Virtex-II Pro architectures. They must be installed on top of the
     ISE™ 8.2i sp1 release.




The Spartan-3/3E are not supported, so how did you do to implement your 
bitstreams ?

I hope that the Spartan-4 will implement partial reconfiguration.

Best Regards,

Guillaume


Justin Braun wrote:
> This group seems relatively inactive recently but I thought I would 
> try to post a few questions about partial reconfiguration on the 
> Spartan-3/3E series devices.
>
> I recently went through the design flow as described in the Early 
> Access Partial Reconfiguration User Guide. I had no problems making a 
> small demo work on two separate Virtex-4 development boards but I 
> could not successfully generate working bitstreams for the a 
> Spartan-3E device. There were no errors until I started to generate 
> the bitsreams. The pr_verifydesign step would generate "frame boundary 
> errors" in the ".summary" output file which Xilinx states:
>
> "Frame boundary errors are likely due to illegal range constraints for 
> the PR region. For
> example, this error occurs if the BRAM range does not match the CLB 
> range. Check to
> ensure that the BRAM range includes all the block RAM elements within 
> the CLB range."
>
> My PR region only contains CLBs and there were no other errors 
> throughout the process.
>
> Is anybody doing partial reconfiguration on Spartan 3/3E devices?
> How can I fix these "frame boundary errors"?
>
> Some information on Xilinx's site about partial reconfiguration on 
> Spartan-3/3E devices has stated, "unmodified bits in a partially 
> reconfigured column in Spartan-3/-3E devices are temporarily reset 
> during the reconfiguration process." Is this valid?
>
> Thanks,
> Justin Braun
>
>
>
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