[partial-reconfig] Partially reconfiguring a readback bitstream

[Enno Luebbers <enno.luebbers@xxxxxxxxxxxxxxxx>]

Hello,

I'm currently investigating methods to implement hardware  
multitasking on a Virtex-II Pro FPGA. One critical problem is  
obviously the saving and restoring of the "context", that is the  
internal state of a hardware module prior to replacement. I was  
thinking about using partial bitstream readback to retrieve the  
module's register and RAM states. If that module is to resume  
operation later, one could easily use the readback frame data to  
partially reconfigure the FPGA with the previous state.

This approach seems pretty straightforward. However, I see an issue  
with the Virtex-II-Pro configuration architecture that would prove  
prohibitive: Usually, when reconfiguring a (complete) FPGA, the IOB  
and CLB register's initialization data embedded in the configuration  
bitstream is loaded _FPGA-wide_ by issuing the GRESTORE command to  
the CMD register. This ensures that all registers that have been  
defined with an initialization value in the VHDL code, e.g.

	...
	signal mySignal : std_logic := '1';
	...

are initialized to that value. When writing an active partial  
bitstream, however, it is my understanding that the GRESTORE command  
can not be used to restore state information, since it would reset  
_all_ FPGA registers to the initial values, not just those in the  
reconfigurable region.

Is there another way to use a partial readback bitrstream (with  
embedded state information) to reprogram the same partially  
reconfigurable region at a later time, in order to restore the  
previous state information?

Best regards,
Enno

--
Dipl.-Ing. Enno Lübbers
Fachgebiet Technische Informatik
Universität Paderborn

Warburger Str. 100
33098 Paderborn

http://wwwcs.upb.de/cs/ag-platzner
Telefon: 05251 / 60-5397
Telefax: 05251 / 60-5377




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