[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [partial-reconfig] Integrating Microblaze with EDK and Planahead
Hi,
Thank you for your input. When I tried to include synthesis/system_bd.bmm and mb0_default/executable.elf using iMPACT, I received the following warning: "IMPACT:1819 - unexpected processor type 2".
In iMPACT where I added my executable.elf file, it specifies "Power PC software files", but I am using a Microblaze for my application. Would this be the source of error??
The following steps are what I have done to generate the full and bit stream. Hopefully they provide the starting steps for others that want to incorporate a Microblaze into their partial reconfiguration design and point out what I have done wrong.
The top.vhd, static.vhd, reconfig.vhd and top.ucf files are attached.
Demo Description:
The Microblaze is connected to the GPIO (1 bit) which is connected to a reconfigurable module that takes this input and simply turns LED1 on (straight thru) and LED2 (invert input signal). The blinking rate is determined by software through the Microblaze. For now, the Microblaze is in a while(1) loop that sends the signal to reconfig via GPIO at a pre-determined rate. The second reconfiguration module (to be implemented) will blink the two LEDs together instead of alternating.
1. Build the system in BSB
- add the reconfig module peripheral
- connect input of reconfig_module to GPIO (1 bit)
- remove DCM (for simplicity only... to be added later)
- verify that demois fully functional.
2. Rename hdl/system_stub.vhd to top.vhd
- replace occurences of "system_stub" with "top"
- replace occurences of "system" with "static"
- remove "reconfig_0_reco_module_led1_pin" and "reconfig_0_reco_module_led2_pin" from static component
- add "opb_gpio_0_GPIO_IO_O" to static component (connected as input of reconfig_module)
- add busmacros (busmacro_xc2vp_r2l_sync_narrow and busmacro_xc2vp_l2r_sync_narrow)
- add "reconfig_module" component
- connect the signals together
- run synthesis - XST
3. Rename hdl/system.vhd to static.vhd
- replace occurences of "system" with "static"
- remove "reconfig_0_reco_module_led1_pin" and "reconfig_0_reco_module_led2_pin" from static component
- add "opb_gpio_0_GPIO_IO_O" to "static" entity (connected as input of reconfig_module)
- remove reconfig component and its port maps (reconfig no longer exists in static.vhd)
- de-select "Add I/O buffer" from Synthesis properties
- run Synthesis - XST
4. Synthesis reconfig.vhd
- de-select "Add I/O buffer" from Synthesis properties
- run Synthesis - XST
5. Create PlanAhead Project
- use top.ngc as top module
- include static.ngc and reconfig.ngc
- include implementation/*.ngc for all wrappers
- include .ucf file
- run DRC check (should pass with no violations)
- make sure *.nmc files are at same location as top.ngc
6. Export Floorplan
- select "partial-config" option
7. Run Partial Configration
7a) Initial budget
- Run with default options
7b) Static Implementation
- Run with default options
- Option to include .BMM file (include it here???? Or use iMPACT??)
7c) PR Block Implementation
- Run with default options except at "Setup Map Options", select "none" for "Flip-flops may be packed into...."
7d) Assemble
- Run with default options
8. Download bitstream
By now I have a "static_full.bit" and "ag_reconfig_module_cv_routed_partial.bit" in the merge directory. Use iMPACT and assign static_full.bit as configuration file. Also include implmentation/system_bd.bmm and mb0_default/executable.elf. When trying to download, gives the following error:
Boundary-scan chain validated successfully.
Getting bit image from data2bram...
INFO:iMPACT:1818 - Elf file 0
INFO:iMPACT - C:/Partial_Reconfig/XPS_GPIO/mb0_default/executable.elf
INFO:iMPACT:1542 - Deleting BMM Mapping object.
INFO:iMPACT:2369 - Deleting D2B Parameter Set object.
INFO:iMPACT:2370 - Creating D2B Parameter Set object...
INFO:iMPACT:1543 - Creating BMM Mapping object...
INFO:iMPACT:1535 - Creating D2B Translate Object...
NOTE: Applying the contents of the elf file required iMPACT
to modify the bitstream in memory only. This modified
bitstream has not been written to a file and the
original bitstream file remain unchanged.
Data2Bram conversion succeeded.
'3':Programming device...
done.
'3': Reading status register contents...
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
legacy input error : 0
status of GTS_CFG_B : 1
status of GWE : 1
status of GHIGH : 1
value of MODE pin M0 : 1
value of MODE pin M1 : 0
value of MODE pin M2 : 1
value of CFG_RDY (INIT_B) : 1
DONEIN input from DONE pin : 1
IDCODE not validated while trying to write FDRI : 0
write FDRI issued before or after decrypt operation: 0
Decryptor keys not used in proper sequence : 0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 0111 1011 1000 0000 0000 0000 0000
INFO:iMPACT:579 - '3': Completed downloading bit file to device.
Getting bit image from data2bram...
INFO:iMPACT:1818 - Elf file 0
INFO:iMPACT - C:/Partial_Reconfig/XPS_GPIO/mb0_default/executable.elf
NOTE: Applying the contents of the elf file required iMPACT
to modify the bitstream in memory only. This modified
bitstream has not been written to a file and the
original bitstream file remain unchanged.
Data2Bram conversion succeeded.
WARNING:iMPACT:1819 - Unexpected processor type 2.
After download, I have no reponses from the Microblaze (suppose to output messages through UART) and both LED1 and LED2 and constantly "ON". Could somebody plz advise me on what I did wrong??
Thank you
Edward Chen
School of Engineering Science
Simon Fraser University
On 8/6/07, Andreas Hofmann <ahofmann@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
Edward Chen schrieb:
Hi,
> However, the processor does not seem to do anything (perhaps no software
> is "loaded")??? Again to keep things simple, I avoided using DCM for now.
You have to initialize the instruction memory of your MicroBlaze. You
can use the EDK to generate an ELF file of your program. The ELF file
must then be merged with the bitstream. You can use data2mem for this
purpose.
If you use iMPACT to configure your FPGA it will take care of the
necessary steps, if you add an BMM file and your ELF file when assigning
a bitstream to your device.
The BMM file is created by PlanAhead when you implemement your design.
Usually it's named system_bd.bmm. This file maps the BRAM instances of
your system to the BRAM blocks of your FPGA.
Caveat:
There's also an system.bmm that is used as a basis for the generation of
the system_bd.bmm. This system.bmm does not include the actual placement
of the BRAMs.
Both files are in a human readable text format and reside in the
implementation sub-directory of an EDK project if the bitstream has been
generated.
Best regards
Andreas
--
Dipl.-Informatiker Andreas Hofmann
Johann Wolfgang Goethe-University Frankfurt am Main
Faculty of Computer Science and Mathematics
Department of Computer Science
Computer Engineering Chair
Robert-Mayer-Straße 11-15
D-60325 Frankfurt am Main
Tel.: +49 69 798-28252
Fax : +49 69 798-22351
___________________________
partial-reconfig mailing list
partial-reconfig@xxxxxxxxxxxxxx
Mailing List Archive :
http://www.itee.uq.edu.au/~listarch/partial-reconfig/
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################
Net sys_clk_pin LOC=AJ15;
Net sys_clk_pin PERIOD = 10000 ps;
#Net sys_clk_pin TNM_NET = sys_clk_pin;
#Net sys_clk_pin IOSTANDARD = LVCMOS25;
Net sys_rst_pin LOC=AH5;
#Net sys_rst_pin IOSTANDARD = LVTTL;
Net sys_rst_pin TIG;
## IO Devices constraints
Net reconfig_0_reco_module_led1_pin LOC = AC4;
Net reconfig_0_reco_module_led2_pin LOC = AC3;
INST "reconfig_0" AREA_GROUP = "AG_reconfig_module" ;
AREA_GROUP "AG_reconfig_module" MODE = RECONFIG;
AREA_GROUP "AG_reconfig_module" RANGE = SLICE_X24Y8:SLICE_X35Y63 ;
AREA_GROUP "AG_reconfig_module" RANGE=TBUF_X24Y8:TBUF_X26Y63, TBUF_X28Y8:TBUF_X34Y63;
AREA_GROUP "AG_reconfig_module" RANGE=MULT18X18_X2Y1:MULT18X18_X2Y7;
AREA_GROUP "AG_reconfig_module" RANGE=RAMB16_X2Y1:RAMB16_X2Y7;
INST "busmacro1" LOC = SLICE_X34Y18;
INST "busmacro2" LOC = SLICE_X34Y40;
INST "static_i" AREA_GROUP = "AG_StaticModule";
#### Module RS232_Uart_1 constraints
Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;
Net fpga_0_net_gnd_pin LOC=G12;
Net fpga_0_net_gnd_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_pin SLEW = SLOW;
Net fpga_0_net_gnd_pin DRIVE = 6;
Net fpga_0_net_gnd_1_pin LOC=D15;
Net fpga_0_net_gnd_1_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_1_pin SLEW = SLOW;
Net fpga_0_net_gnd_1_pin DRIVE = 6;
Net fpga_0_net_gnd_2_pin LOC=E15;
Net fpga_0_net_gnd_2_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_2_pin SLEW = SLOW;
Net fpga_0_net_gnd_2_pin DRIVE = 6;
Net fpga_0_net_gnd_3_pin LOC=G10;
Net fpga_0_net_gnd_3_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_3_pin SLEW = SLOW;
Net fpga_0_net_gnd_3_pin DRIVE = 6;
Net fpga_0_net_gnd_4_pin LOC=E10;
Net fpga_0_net_gnd_4_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_4_pin SLEW = SLOW;
Net fpga_0_net_gnd_4_pin DRIVE = 6;
Net fpga_0_net_gnd_5_pin LOC=G8;
Net fpga_0_net_gnd_5_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_5_pin SLEW = SLOW;
Net fpga_0_net_gnd_5_pin DRIVE = 6;
Net fpga_0_net_gnd_6_pin LOC=H9;
Net fpga_0_net_gnd_6_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_6_pin SLEW = SLOW;
Net fpga_0_net_gnd_6_pin DRIVE = 6;
Attachment:
static.vhd
Description: Binary data
Attachment:
top.vhd
Description: Binary data
Attachment:
reconfig.vhd
Description: Binary data