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[partial-reconfig] Spartan-3/3E partial reconfiguration
http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2007/07/msg00005.html
Ron Sass wrote :
Hi Justin,
I know almost nothing about the Spartan devices and I'm not
sure if Xilinx has gone into detail documenting these things.
But here's my take on the situation and some of it is speculative.
The Spartan devices are similar but not the same as Virtex
devices. I believe the idea was to make smaller, higher yield
devices. This allows Xilinx to sell them cheaper. That means
removing some transistors and some functionality.
* My guess
is that "glitchless" partial reconfiguration was one of those
functionalities that was sacraficed. *
Basically, configurations
are streamed in serially as they go up a column of the device
and you can save transistors if you assume that column is not
actively doing any useful. (I.e., every configuration transistor
can toggle arbitrarily as long as it is in the proper state when
the device becomes active.) "Useful" includes simply propagating
a signal through a switchbox.
So if one conservatively assumed that a set of columns was
isolated from the rest of the design -- for example, the left
half of the chip -- then partial reconfiguration is possible on
a Spartan. However, partially reconfiguring a smaller region
will almost certainly lead to random failures that would be
impossibly hard to identify. This assumption is why the Erlang
people suggest that to do partial reconfiguration, you need to
have configurability in the PCB design: a column includes IOBs
on the top and bottom which control exernal pins.
So having bus macros for the Spartan is not unreasonable. In a
limited sense partial reconfiguration is possible. I suspect
that the error message means exactly what says: you are trying to
reconfigure something less than the smallest reconfigurable unit.
(In this case, I am guessing you are trying to reconfigure less
than the whole column on a Spartan device.)
Does this make sense? Anyone else have something more fact-based
than my guesses?
Good luck, Justin! And, please share your successes!
Ron
All right, Ron :) !
http://www.xilinx.com/bvdocs/appnotes/xapp452.pdf
*SNOWPLOW Register*
The SNOWPLOW register must be used to partially reconfigure the device
without power-
cycling. Because the Spartan-3 device’s SNOWPLOW reconfiguration is
column-based instead
of frame-based as supported by VirtexTM, Virtex-E, Virtex-II, and
Virtex-II ProTM devices, the
Spartan-3 output is not glitchless during partial reconfiguration.
*Partial Reconfiguration*
At times, it might be desired to reconfigure the LUT function or the
contents of the memory
element, such as SRL16, LUT RAM, or BRAM without power-cycling the
board. The process of
partially reconfiguring Spartan-3 devices without power-cycling is
possible through the use of
SNOWPLOW register.
Although partial reconfiguration is feasible, modular-based partial
reconfiguration is not yet
supported. For the latest modular-based partial reconfiguration, refer
to XAPP290, "Two Flows
for Partial Reconfiguration: Module Based or Difference Based".
Another limitation of partial reconfiguration is it must be performed on
a column basis as
opposed to a frame basis, as supported by the Virtex architecture. As a
result of column-based
reconfiguration, logic outputs might not be glitchless during partial
reconfiguration. Spartan-3
devices also do not have ICAP components.
The following sequence performs partial reconfiguration with the
SNOWPLOW register:
1. Issue a SYNC WORD.
2. Issue any optional commands, such as SHUTDOWN or AGHIGH.
3. WRITE the FAR register with the starting address of the partial
reconfiguration. Since
Spartan-3 devices only support column-based reconfigurations, the
starting address has to
be the first frame address of the starting column.
4. WRITE the SNOWPLOW register with how many columns are reconfigured
(only bits [7:0]
are used).
5. WRITE 16 NOP commands to wait for an internal reset of the first
targeted column.
6. Start reconfiguration.
7. Issue any optional commands, such as START or DGHIGH.
8. Issue a DESYNCH command.
CRC checking is performed for the SNOWPLOW register.
Best Regards,
Guillaume
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