[partial-reconfig] Can global clocks pass through bus macro?

[lipeng <lipeng.net@xxxxxxxxx>]

Hi all,

In xilinx's partial reconfiguration user guide, global clocks needn't pass through bus macros. However, in the reference design, I find clock pass the bus macro. 

In my design, I let clock pass the bus macro, as the ref. design did, but it failed to pass the DRC, a violation was detected:

Name? ?PRPN #1? 
Type? ?Prohibited net through bus macro? 
Description? ?Bus macro led_socket_0/U3_R2L_BM located in SLICE_X26Y136 connects to net clk_in of type CLOCK. This is prohibited.

I dont know if this violation is caused by clock passing bus macro. Can anyone point it out for me?

Thanks.
-- 
Peng