Hi,
Type? ?Prohibited net through bus macro?Description? ?Bus macro led_socket_0/U3_R2L_BM located in SLICE_X26Y136 connects to net clk_in of type CLOCK. This is prohibited. I dont know if this violation is caused by clock passing bus macro. Can anyone point it out for me?
It very much looks like it. For 'regular' (i.e. non-clock) signals, you need (LOC'ed) bus macros so that the "connection points" between your static logic and your partial modules stay fixed between configurations. As long as you LOC your clock buffers, they will always use the same global clock net, so there's no need for passing them through bus macros (which would seriously complicate timing). That's probably why the Xilinx tools prohibit it.
Best, Enno -- Dipl.-Ing. Enno Lübbers Fachgebiet Technische Informatik Universität Paderborn Warburger Str. 100 33098 Paderborn http://wwwcs.upb.de/cs/ag-platzner Telefon: 05251 / 60-5397 Telefax: 05251 / 60-5377 ___________________________ partial-reconfig mailing list partial-reconfig@xxxxxxxxxxxxxx Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/