Hi, If you read through the previous reply in this email, you will see the link to the partial reconfiguration lounge. At there you will see the examples, docs, and tools. This is the link: http://www.xilinx.com/support/prealounge/protected/archive_82.htm Have a nice weekend, Thang Nguyen -----Original Message----- From: owner-partial-reconfig@xxxxxxxxxxxxxx on behalf of Wei Sun Sent: Tue 9/11/2007 7:05 AM To: partial-reconfig@xxxxxxxxxxxxxx Subject: Re: [partial-reconfig] Simple partial reconfiguration basci system example Hi, I am new to partial reconfiguration but it's definitely an interesting topic. As there is no official, good example yet, can we work together to make such a design in a open source way? Everyone can benefit from it. Greetings, Sunwei On 9/8/07, lipeng <lipeng.net@xxxxxxxxx> wrote: > > I don't think the EDK reference design published by Xilinx is a good one. > It neglects the part I mostly concern: how are partial modules imported > into EDK > It just offers implemented pcores, and guides you to copy them to the > project directory. > > On 9/6/07, Andreas Hofmann <ahofmann@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> > wrote: > > > > Hello, > > > > I'm also working on partial reconfiguration using a Virtex4-FX20 > > device(ML405). As I only have ISE/EDK 8.1 available at the moment, whose > > HWICAP does not support V4 device, I extracted the HWICAP updates from > > the latest EDK 9.1 service pack. But, too, I was only successful to read > > out the status registers. When I send a partial bitstream to the HWICAP > > device, no reconfiguration takes place and the CRC-Error bit is set in > > the status register. This explains why no reconfiguration takes place. > > When writing the same partial bitstream via iMPACT to the FPGA all is > > fine. > > > > The Xilinx HWICAP driver are plain C. You can have a look at their > > source code which is located in > > > > %EDK%\sw\XilinxProcessorIPLib\drivers\hwicap_* > > > > Furthermore, Xilinx has published a new reference design for partial > > reconfiguration: > > > > http://www.xilinx.com/support/prealounge/protected/archive_82.htm > > > > Quote: "Virtex 4 EDK design with a Microblaze processor. The partially > > reconfigurable filters are peripherals of the Microblaze processor. > > Target hardware is the Virtex ML401 development board." > > > > Best regards, > > Andreas > > > > Fabian Schulte schrieb: > > > Hello to everyone and especially Elisa and Vincent, > > > I tried do build such a System with a PPC and the ICAP Interface. But > > I > > > could only read out the IDCODE register. A partial reconfiguration > > (with > > > the set_Configuration function of the EDK HWICAP driver) was not > > > successful. I already wrote a Message to this Mailing list on > > 26.07.2007. > > > > > > If one of you has such a System with a microcontroller and ICAP, i > > was > > > very thankful for any hints or Code fragments. > > > > > > Thank you very much. > > > Fabian Schulte > > > > -- > > Dipl.-Informatiker Andreas Hofmann > > > > Johann Wolfgang Goethe-Universität Frankfurt am Main > > > > Fachbereich Informatik und Mathematik > > Institut für Informatik > > Professur für Technische Informatik > > > > Robert-Mayer-Straße 11-15 > > D-60325 Frankfurt am Main > > > > Tel.: +49 69 798-28252 > > Fax : +49 69 798-22351 > > ___________________________ > > partial-reconfig mailing list > > partial-reconfig@xxxxxxxxxxxxxx > > Mailing List Archive : > > http://www.itee.uq.edu.au/~listarch/partial-reconfig/<http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/> > > > > > > -- > Peng Li, > Institute of Computing Technology, > Chinese Academy of Sciences, > Beijing, P. R. China.
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