Hi all,
I used EAPR to achieve DPR, and followed "Early Access Partial Reconfiguration User Guide". But at step 6, Implement PR modules, I met the following error
> par -w top.ncd PRM_or.ncd
Release 9.1.02i_PR2 - par JTRS.J32
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Physical Constraints file: top.pcf.
Loading device for application Rf_Device from file '4vlx25.nph' in environment F:\Xilinx91i.
"top" is an NCD, version 3.1, device xc4vlx25, package sf363, speed -12
This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com
.
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.63 2007-01-26".
Device Utilization Summary:
Number of External IOBs 6 out of 240 2%
Number of LOCed IOBs 6 out of 6 100%
Number of Slices 1 out of 10752 1%
Number of SLICEMs 0 out of 5376 0%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
WARNING:Par - UCF constraints file not found.
For partial reconfiguration flow this is required to support
relocatable bit streams. If you wish to utilize relocatable
bit streams then you must have the UCF file available.
INFO: Partial Reconfig: Utilizing file "arcs.exclude" for P&R info.
Resolving Placement Constraints.
Place Locked Logic.
Writing design to file PRM_or.ncd
ERROR: Net a2_IBUF crosses a region boundary and is not part of a slice macro.
Nets crossing region boundaries must be part of a slice macro
Static: a2
Module: out2_OBUF
ERROR: Net b2_IBUF crosses a region boundary and is not part of a slice macro.
Nets crossing region boundaries must be part of a slice macro
Static: b2
Module: out2_OBUF
ERROR: Net out2_OBUF crosses a region boundary and is not part of a slice macro.
Nets crossing region boundaries must be part of a slice macro
Static: out2
Module: out2_OBUF
The logic of PRM is out2<=a2 or b2
Does anyone know how to solve the problem?
Thanks,
Jin Xi