[partial-reconfig] BusMacros...

["Elisa Giani" <ely78max@xxxxxxxxx>]

Hi,
could you give instructions to use the sync version of BM  ?

component busmacro_xc4v_l2r_sync_narrow is
        port (
            input0 : in std_logic;
            input1 : in std_logic;
        input2 : in std_logic;
            input3 : in std_logic;
        input4 : in std_logic;
            input5 : in std_logic;
        input6 : in std_logic;
            input7 : in std_logic;
        ce0 : in std_logic;
            ce1 : in std_logic;
        ce2 : in std_logic;
            ce3 : in std_logic;
        clk0 : in std_logic;
            clk1 : in std_logic;
        clk2 : in std_logic;
            clk3 : in std_logic;
            output0 : out std_logic;
            output1 : out std_logic;
        output2 : out std_logic;
            output3 : out std_logic;
        output4 : out std_logic;
            output5 : out std_logic;
        output6 : out std_logic;
            output7 : out std_logic
        );
    end component;

I think my problem came from bad sync of signals throught static and dynamic design...

Another solution are the constraints like this..
NET "LED6_OBUF_PN" TPSYNC = "BM_out_7_LED6_OBUF_PN"; 
TIMEGRP "BM_out_7_LED6_OBUF_PN" OFFSET = IN <constraint> BEFORE <clkName>;

ELy

2007/10/9, Mark Harvey <mark.harvey@xxxxxxxxxx>:

 

---

From: Elisa Giani [mailto:ely78max@xxxxxxxxx]
Sent: 09 October 2007 10:36
To: Mark Harvey
Subject: BusMacros...

Hi Mark,
I've implemented a complete partial reconfigurable system , but I think there are some problems with the value of some signals that come out from dynamic region and go into static part.
The value of this signals is undeterminated during reconfiguration process?  

 

Yes. 

I see exist some BM with enable...but this enable must be handled by static part , I think... 

 

Yes. 

In my design I've a state machine that enable a module and wait for an acknowledge from it.
When module answers , the state machine changes state.

But if during reconfiguration process the aknowledgement signal from module change value, the state machine could find knowledgement signal active(1) when the module has not been reconfigured jet...  

How can I resolve this ?  

 

..you need to handle this in the static logic. 

Ely