Hi, I am working with building a custom core and integrate it with the embedded system on the Virtex II Pro Platform. I am using ISE 8.2i. Make it simple, I will use an example here: I used Create/import peripheral wizard to create a core name: plb_fpu which has 5 32-bit registers. I made myself a module called fpu.vhd In this fpu.vhdl, I have 4 modules: add.vhd, sub.vhd, mul.vhd, div.vhd. After simulating of each module and the fpu module, I start to integrate this module into my core. But when I synthesized my core, I have error for all output signals: The error I have is: ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg3<31>> Sources are: Output signal of FD instance <USER_LOGIC_I/i_fpu1/output_o_0> Output signal of FDRE instance <USER_LOGIC_I/slv_reg3_31> ...... I did add all the .vhd files into the vhdl folder inside the pcore and add the name of these files in the .pao file. But the error still happens. I expect you who have a lot of experiment with building and integrating the core help me on this issue. I highly appreciate your time of reading and answering my question. Thang Nguyen
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