Re: [partial-reconfig] need help with integrating custom core into embedded system

[Andreas Hofmann <ahofmann@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>]

Nguyen, Thang Toan wrote:

Hi,

> The error I have is:
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg3<31>>
> Sources are:
>    Output signal of FD instance <USER_LOGIC_I/i_fpu1/output_o_0>
>    Output signal of FDRE instance <USER_LOGIC_I/slv_reg3_31>
>
> ......

this looks like a vhdl coding error and should not be related to
something EDK specific.

How do you connect your fpu module to the 5 registers of the  plb core?

If you create a core with registers the EDK automatically generates
processes to read and write these registers. So if you connect the fpu
module output to slv_reg3 you will have at least two drivers for this
register: the output of your fpu module and the write process of the plb
core. That's what Xst is reporting in your case.

If slv_reg3 should be read only as seen from the plb you can just remove
the part of the SLAVE_REG_WRITE_PROC_write process that writes to slv_reg3.

Regards,
Andreas

-- 
Dipl.-Informatiker Andreas Hofmann

Johann Wolfgang Goethe-University Frankfurt am Main

Faculty of Computer Science and Mathematics
Department of Computer Science
Computer Engineering Chair

Robert-Mayer-Straße 11-15
D-60325 Frankfurt am Main

Tel.: +49 69 798-28252
Fax : +49 69 798-22351
___________________________
partial-reconfig mailing list
partial-reconfig@xxxxxxxxxxxxxx
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/