when I do reconfiguration using EAPR, I meet a incredible problem.
I create my project using EDK. The plb_ddr is included in the project. When I do reconfiguration, the plb_ddr is included in base.The cmd.exe shows the informations as follow while mapping the base:
=========================================================================
Release 9.1.02i_PR2 - Map JTRS.J32
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Using target part "2vp30ff896-5".
Mapping design into LUTs...
Writing file top.ngm...
Running directed packing...
ERROR:Pack:626 - The dual data rate register
u0/ddr_512mb_64mx64_rank2_row13_col10_cl2_5/ddr_512mb_64mx64_rank2_row13_col1
0_cl2_5/WO_ECC.DDR_CTRL_I/CLKGEN_I/NOT_VIRTEX4_IOREGS.GEN_CLK_PAIR_N[3].DDR_C
LKN_REG_I failed to join an I/O component as required. Please try
constraining the register together with a valid pad or output buffer symbol.
Note that FDDR library symbols may drive output buffers only.
Mapping completed.
See MAP report file "top.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 7
=====================================================================
How to solve this problem? Thanks!