Hi! Everyone:
My target board is the Xilinx ML310, which contains a Virtex-II Pro XC2VP30 FPGA. I followed the EAPR flow and successfully generated my partial bitstreams. My system architecture was created by using the EDK tool, where the clock signals of all the DPR modules were transferred through a gloabal buffer (BUFG) and the HWICAP provided by the EDK was used in my system architecture. My partial bitstreams can successfully work by using the iMPACT tool over JTAG, but only the partial bitstreams for the combinational circuits can successfully work by using the ICAP. My partial bitstreams for the sequence circuits cannot successfully be reconfigured by using the ICAP. I am very confused with the above problem. Is there something that I have to consider when I use the ICAP? Similar to the general signals connected to the DPR modules, my reset signal is connected to the DPR module by using the busmacro provided by Xilinx. Is the connection method of the DPR modules for clock and reset signals right?
Besides, I used the "ncd2xdl" command to transform my "nmc" file of busmacro to the "xdl" file, and then transfromed the "xdl" file back to nmc file ("xdl2ncd" command) without modifying its content. The original nmc file was 11 KB, but the new nmc file was only 4 KB and cannot be used like the original busmacro file. My ISE version is 8.2. Is there anything that I have to modify for the ISE tool? Or which ISE version can work correctly? Here are my questions. Can someone help me? Thanks very much!
Best Regards,
Huang