[partial-reconfig] Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4)

[Gaël ABGRALL <Gael.Abgrall@xxxxxxxxxx>]

Hello everybody, 

Let me introduce myself, I'm a PhD student
at the ENSIETA (Brest, France) and I work on Partial Reconfiguration (and
also on SCA and Network-on-Chip).

I try to do the tutorial provided by
Xilinx which is : "PR Flow Design Examples Using ISE 9.1.2 with PR10
Overlay Targeting ML403 Board".

I have no problem with the first tutorial (Command Line PR Implementation Flow) but for the others PlanAhead must be used and I have some problems with it.

When I try to do the step 6 (Run PR Implementation Flow) on tutorial 2, I must use "Launch Run" to run the static implementation. After this, the status of the run become "Queued" and there is nothing happen after this.

I don't know what it could be, if anyone have already meet this problem, it will be great if you can help me.

Regards,

Gael Abgrall.
--------------------------------------------------------

Gael ABGRALL
Doctorant
Laboratoire DTN / CSE
ENSIETA
2 rue François Verny
29806 Brest cedex 9

Bureau : E 116
Tel : (0/33) 2 98 34 88 91
E-mail : gael.abgrall@xxxxxxxxxx