RE: [partial-reconfig] ICAP on Virtex II Pro and ML310

["Mati Nahshon" <mati.nahshon@xxxxxxxxx>]

Hi,
It's been long time since I worked on it but just some points that may help:
- all signals are active low
- Big endian bytewize = to write AA995566 do:
AA
99
55
66
- not every thing is documented try adding 20000000 if things don't work.
- Abort status word is presented on ICAP_O[4:7] while read is not performed
(this is not documented) this can help during debug (look for errors are
status during operation)
- make sure you are not violating the abort rule (double check).
- are you waiting long enough?

Mati

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Bollo Davide
Sent: Wednesday, May 07, 2008 12:40 AM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: [partial-reconfig] ICAP on Virtex II Pro and ML310

Hi all, i'm newbie!

I'm working on a State Machine to command directly ICAP interface on a
Virtex II Pro XCV2P30 on a ML310 board.

I'd followed instruction on UG012, User Guide by Xilinx about SELECT MAP
communication Protocol. I know that Select Map DATAPORT have "0" as MSB, so
ICAP have "7" as MSB.

I made a State Machine in VHDL code, to command ICAP interface, and read
IDCODE from my device, with these step:

        CE    WR        WORD
1        1        0

2        0        0        FFFFFFFF		Dummy word
3        0        0        AA995566		synch
4        0        0        2801C001		read 1 word from IDCODE
5        0        0        20000000		flush word
6        0        0        20000000

7        1        0                       (here busy goes HIGH)
8        1        1
9        0        1                       waiting for busy=0 --> read word
(4 CK) --> go to the next state

10      1        1
11      1        0
12      0        0

13      0        0        0000000D    desynch
14      0        0        20000000
15      0        0        20000000

Every write-word step is splitted in 4 substeps.
Machine works good on simulation (with busy simulation too).

I snoop signal with Chipscope, with ILA core insertion on every icap signal.


My machine goes on step 9 and wait here forever.
Why BUSY doesn't return down?
Where is my mistake?

Some information:
	Icap_clock= 10 Mhz
	Ise 7.1, Chipscope 7.1 (old but i can't work only with this)
	download bitstream configuration on JTAG chain, with chipscope.
	M0:M2 = 111

I hope in your help!


Davide
	


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