RE: [partial-reconfig] ICAP on Virtex II Pro and ML310

["Mati Nahshon" <mati.nahshon@xxxxxxxxx>]

I am sorry I wont have my notes for a few days but in the mean time if I see
correctly in the chipscope you did not succeed in sending the sync word your
abort status is 0x9 if I remember correctly after sending the sync word it
should change to 0xD or something. Try adding 20000000 (or deasserting CE)
until you get synced and before you send any command.
Mati
-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of
il-guru@xxxxxxxxxxx
Sent: Wednesday, May 07, 2008 1:13 PM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: Re: [partial-reconfig] ICAP on Virtex II Pro and ML310

ok i knowed that.
i supposet CE and WR active low.

please, can you see my chipscope screenshot and tell me my 
mistake?
acquired.jpg


On Wed, 7 May 2008 12:15:33 +0300
  "Mati Nahshon" <mati.nahshon@xxxxxxxxx> wrote:
> Control singals are active low
> 
> -----Original Message-----
>From: owner-partial-reconfig@xxxxxxxxxxxxxx
> [mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf 
>Of
> il-guru@xxxxxxxxxxx
> Sent: Wednesday, May 07, 2008 10:50 AM
> To: partial-reconfig@xxxxxxxxxxxxxx
> Subject: Re: [partial-reconfig] ICAP on Virtex II Pro 
>and ML310
> 
> oh sorry i didn't explain:
> on write-word status i send to icap_in port 1 byte @ 
>time.
> so 32bit word is divided in 4 byte words.sorry
> 
> i'm sure to not violating abort sequence (i change WR 
>only 
> on CE=1).
> 
> i've tried to wait for 16k clock cycles...but my BUSY 
> doesn't change.
> 
> you said "all signals are active-low". ICAP_IN too?
> 
> thanks.
> Davide
> 
> 
> On Wed, 7 May 2008 02:07:36 +0300
>  "Mati Nahshon" <mati.nahshon@xxxxxxxxx> wrote:
>> Hi,
>> It's been long time since I worked on it but just some 
>>points that may help:
>> - all signals are active low
>> - Big endian bytewize = to write AA995566 do:
>> AA
>> 99
>> 55
>> 66
>> - not every thing is documented try adding 20000000 if 
>>things don't work.
>> - Abort status word is presented on ICAP_O[4:7] while 
>>read is not performed
>> (this is not documented) this can help during debug 
>>(look for errors are
>> status during operation)
>> - make sure you are not violating the abort rule (double 
>>check).
>> - are you waiting long enough?
>> 
>> Mati
>> 
>> -----Original Message-----
>>From: owner-partial-reconfig@xxxxxxxxxxxxxx
>> [mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf 
>>Of Bollo Davide
>> Sent: Wednesday, May 07, 2008 12:40 AM
>> To: partial-reconfig@xxxxxxxxxxxxxx
>> Subject: [partial-reconfig] ICAP on Virtex II Pro and 
>>ML310
>> 
>> Hi all, i'm newbie!
>> 
>> I'm working on a State Machine to command directly ICAP 
>>interface on a
>> Virtex II Pro XCV2P30 on a ML310 board.
>> 
>> I'd followed instruction on UG012, User Guide by Xilinx 
>>about SELECT MAP
>> communication Protocol. I know that Select Map DATAPORT 
>>have "0" as MSB, so
>> ICAP have "7" as MSB.
>> 
>> I made a State Machine in VHDL code, to command ICAP 
>>interface, and read
>> IDCODE from my device, with these step:
>> 
>>        CE    WR        WORD
>> 1        1        0
>> 
>> 2        0        0        FFFFFFFF		Dummy word
>> 3        0        0        AA995566		synch
>> 4        0        0        2801C001		read 1 word from 
>>IDCODE
>> 5        0        0        20000000		flush word
>> 6        0        0        20000000
>> 
>> 7        1        0                       (here busy 
>>goes HIGH)
>> 8        1        1
>> 9        0        1                       waiting for 
>>busy=0 --> read word
>> (4 CK) --> go to the next state
>> 
>> 10      1        1
>> 11      1        0
>> 12      0        0
>> 
>> 13      0        0        0000000D    desynch
>> 14      0        0        20000000
>> 15      0        0        20000000
>> 
>> Every write-word step is splitted in 4 substeps.
>> Machine works good on simulation (with busy simulation 
>>too).
>> 
>> I snoop signal with Chipscope, with ILA core insertion 
>>on every icap signal.
>> 
>> 
>> My machine goes on step 9 and wait here forever.
>> Why BUSY doesn't return down?
>> Where is my mistake?
>> 
>> Some information:
>> 	Icap_clock= 10 Mhz
>> 	Ise 7.1, Chipscope 7.1 (old but i can't work only with 
>>this)
>> 	download bitstream configuration on JTAG chain, with 
>>chipscope.
>> 	M0:M2 = 111
>> 
>> I hope in your help!
>> 
>> 
>> Davide
>> 	
>> 
>> 
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> 
> 
> --------------------------------------------------------------------------
> Hai tempo fino al 31/03/2008 per azzerare i costi di 
>attivazione:
> da casa o dall'ufficio naviga con la qualità di Infinito 
>ADSL
> (www.infinito.it/adsl)
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--------------------------------------------------------------------------
Hai tempo fino al 31/03/2008 per azzerare i costi di attivazione:
da casa o dall'ufficio naviga con la qualità di Infinito ADSL
(www.infinito.it/adsl)


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