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Hey,
I've gone through the Xilinx design labs for
ML401 board OPB_hwicap. I have some questions related to lab 4.
1) What is the purpose of opb_socket_bridge
and opb_prr cores?
2) At what part of the design phase do I have to use the bus macros?
Additionally, I plan on designing almost same
kind of system but with PLBv46 compliant peripherals. A friend
would design these cores using system generator. If anyone has
performed partial reconfiguration of PLBv46 compliant peripherals using the
xps_hwicap core then his/her guidance would be of great help and highly
appreciated. And I know it's a lot to ask, but could anyone please give me (or guide me to design) the cores that
work with this bus interface and perform the same functionality as the
opb_prr and opb_socket_bridge cores did in lab 4? I understand that I'll have to
use the plb2dcr_bridge in place of opb3dcr_bridge in my design.
Alternatively, if everything else fails, I plan to design opb compliant
peripherals by appending the HDL code from the system generator in my cores. =(
Any guidance would make yours truly tearful with gratitude. =)
Regards,
M.Omer |