Hello All,
I am trying to design a partial reconfiguration system by loading bitstreams
from SysACE to ICAP. My design includes the Microblaze processor and I am using
the Virtex 5 (ML501) evaluation kit. I am using ISE 9.2+SP 4 and EDK 9.2+SP 2
along with PlanAhead 10.1.4. I followed the design process from the math example
that is provided on the Xilinx web.
I am able to generate the bitstreams and load the full bitstream. But, when I try
to partially reconfigure the system, the processor just hangs. I included
#define DEBUG 1
and this shows that the bitstream is being read from the CF card and passed
onto ICAP. I waited for atleast 30 minutes and it still kept reading the
bitstream but nothing happened. My partial bitstreams are around 100KB in size.
One more peculiar problem I see is that when I press the reset button on the
board after the processor hangs, nothing seems to happen. The processor does
not reset itself.
Could this be a clocking problem? I place all my DCM modules
in the top level design. Is there a particular region on the FPGA, when
floorplanning in PlanAhead, where I need to specify the area constraints for
the partial reconfiguration modules?
Or could this be a problem with the HWICAP core?
I would really appreciate it if anyone could help me out as I am on a tight
deadline.
Thank you,
Adarsha