RE: [partial-reconfig] Problem with partial reconfiguration on ML501

["Adarsha Sreeramareddy" <adarshs@xxxxxxxxxxxxxxxxx>]

OK, it seems like my partial bitstreams are not working when I load it
through the JTAG too. The processor just hangs when I do a partial
reconfiguration through JTAG. Initially I thought the partial bitstreams
were loading since IMPACT gave a Programming Succeeded message. So I did not
bother to verify it.

Does anyone have any suggestions?

Thanks,
Adarsha

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Adarsha
Sreeramareddy
Sent: Tuesday, November 04, 2008 2:54 AM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on
ML501

Mati,

I tried using PlanAdead 10.1.8, but with no success. Do you have any other
ideas? Should I limit the ICAP frequency to 100 MHz? If so, how do I do it
in EDK?

Should I also specify any ICAP constraint in the UCF file?

Thanks,
Adarsha

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Adarsha
Sreeramareddy
Sent: Monday, November 03, 2008 12:59 PM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on
ML501

I am using the same ICAP and driver versions as in the tutorial. It is
xps_hwicap v1.00.a and driver v2.00.a.

Thanks,
Adarsha

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Lu Yi
Sent: Monday, November 03, 2008 3:05 AM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on
ML501

 I dont know which version of the ICAP and its driver you used, did you use
the same version as in the tutorial?

R.
luyi

> Hi Mati,
>
>
>
> I ran the Math tutorial from the Xilinx website with the current 
> toolset and it works fine. But, when I try incorporating my own PR 
> modules, it gives me the problem. Also, I can load the partial 
> bitstreams successfully through JTAG for my design.
>
>
>
> Thanks,
>
> Adarsha
>
>
>
> From: owner-partial-reconfig@xxxxxxxxxxxxxx
> [mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Mati 
> Nahshon
> Sent: Sunday, November 02, 2008 2:46 PM
> To: partial-reconfig@xxxxxxxxxxxxxx
> Subject: RE: [partial-reconfig] Problem with partial reconfiguration 
> on
> ML501
>
>
>
> I don't know if this is relevant but you should use PlanAhead 10.1.8
>
>
>
> Mati Nahshon
> Electronics Engineer,
> Consultant.
>
> ____________________________
> Cell:     +972-54-7647107
> E-Mail: nahshon.mati@xxxxxxxxx
>
> ____________________________
>
>   _____
>
> From: owner-partial-reconfig@xxxxxxxxxxxxxx
> [mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Adarsha 
> Sreeramareddy
> Sent: Sunday, November 02, 2008 10:24 PM
> To: partial-reconfig@xxxxxxxxxxxxxx
> Subject: [partial-reconfig] Problem with partial reconfiguration on
> ML501
>
>
>
> Hello All,
>
> I am trying to design a partial reconfiguration system by loading 
> bitstreams from SysACE to ICAP. My design includes the Microblaze 
> processor and I am using the Virtex 5 (ML501) evaluation kit. I am 
> using ISE 9.2+SP 4 and EDK 9.2+SP 2 along with PlanAhead 10.1.4. I 
> followed the design process from the math example that is provided on 
> the Xilinx web.
>
> I am able to generate the bitstreams and load the full bitstream. But, 
> when I try to partially reconfigure the system, the processor just 
> hangs. I included #define DEBUG 1 and this shows that the bitstream is 
> being read from the CF card and passed onto ICAP. I waited for atleast 
> 30 minutes and it still kept reading the bitstream but nothing 
> happened. My partial bitstreams are around 100KB in size.
>
> One more peculiar problem I see is that when I press the reset button 
> on the board after the processor hangs, nothing seems to happen. The 
> processor does not reset itself.
>
>
>
> Could this be a clocking problem? I place all my DCM modules in the 
> top level design. Is there a particular region on the FPGA, when 
> floorplanning in PlanAhead, where I need to specify the area 
> constraints for the partial reconfiguration modules?
>
>
>
> Or could this be a problem with the HWICAP core?
>
> I would really appreciate it if anyone could help me out as I am on a 
> tight deadline.
>
> Thank you,
> Adarsha
>
>

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