[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: [partial-reconfig] Problem with partial reconfiguration on ML501

To: <partial-reconfig@xxxxxxxxxxxxxx>
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on ML501
From: "Mati Nahshon" <mati.nahshon@xxxxxxxxx>
Date: Tue, 4 Nov 2008 17:56:48 +0200
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:references:subject :date:message-id:mime-version:content-type:content-transfer-encoding :x-mailer:x-mimeole:thread-index:in-reply-to; bh=zV/vwO8S480JVBkLfEqOZheQJw29TmPSr86VhsBnDDo=; b=tTgxkHo55bRf71T5W01qh46XVtdnXuhBk43UF0siYSAqoPaR8iJHW5ulHFvb/OMAq1 5yt0A9EtrZJFETrfiHPgoUw7gyMFz6uQtmhlgK6B9JvZMPQbYn2Q0qNkRxBlfedJOxLo 4+ZlZw8K5BlmUJ86OZ+mnUZ9GpPjDVwv/WuWI=
Domainkey-signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:references:subject:date:message-id:mime-version :content-type:content-transfer-encoding:x-mailer:x-mimeole :thread-index:in-reply-to; b=XP0mrbr3L9VWibdmkzvtt9j9/4A8Rk5ajLRBi2ukno058xRMlGnhLB8Sj3KFuqx4iS /+FZjnWDPmNhKqEPHg60FRNJxxV1P3/kGWZS0Q3t953QDb4hA9UV3UKD1VDi2UJkqRyG HUSNXhRkgbU86pWLKtHEpSQbT7PT2hCCjwboQ=
In-reply-to: <002b01c93e63$537aa200$fa6fe600$@arizona.edu>
References: <000001c93d28$f81e6ee0$e85b4ca0$@arizona.edu> <6774BFAA799548499399C31EB1DD99E0@MATILAPTOP> <000b01c93d35$a6cfb140$f46f13c0$@arizona.edu> <3689.130.161.38.7.1225706704.squirrel@xxxxxxxxxxxxxxxxxxxxx> <002301c93dee$9e0b9600$da22c200$@arizona.edu> <002b01c93e63$537aa200$fa6fe600$@arizona.edu>
Reply-to: partial-reconfig@xxxxxxxxxxxxxx
Sender: owner-partial-reconfig@xxxxxxxxxxxxxx
Thread-index: Ack9nSUyD+JCJL1lTX2pDuJAm5w4xAAUTCAAAB0UJWAADK+gMA==

As far as I know ICAP will not work faster than 100 MHz even with V5, I
checked it with Virtex 4 running at 100 and it did...
Please check the other issues but I think (without checking ) that the bus
(PLB/OPB) must not run at higher than 100 MHz.

Mati

+/v8APAAh-DOCTYPE HTML PUBLIC +ACI--//W3C//DTD HTML 4.0
Transitional//EN+ACIAPg- +ADw-HTML XMLNS:U1 xmlns:st1 +AD0-
+ACI-urn:schemas-microsoft-com:office:smarttags+ACIAPgA8-HEAD+AD4APA-TITLE+A
D4-Mati Signature+ADw-/TITLE+AD4- +ADw-META http-equiv+AD0-Content-Type
content+AD0AIg-text/html+ADs- charset+AD0-utf-7+ACIAPg- +ADw-META
content+AD0AIg-MSHTML 6.00.6000.16705+ACI-
name+AD0-GENERATOR+AD4APA-/HEAD+AD4- +ADw-BODY+AD4- +ADw-DIV dir+AD0-ltr
align+AD0-left+AD4APA-SPAN style+AD0AIg-FONT-WEIGHT: bold+ADs- COLOR:
navy+ADs- FONT-FAMILY: Arial+ACIAPgA8-/SPAN+AD4APA-STRONG+AD4APA-FONT
face+AD0-Arial color+AD0AIw-000080+AD4-Mati
Nahshon+ADw-/FONT+AD4APA-/STRONG+AD4APA-BR+AD4APA-B+AD4APA-FONT
face+AD0-Tahoma color+AD0-navy size+AD0-2+AD4APA-SPAN
style+AD0AIg-FONT-WEIGHT: bold+ADs- FONT-SIZE: 10pt+ADs- COLOR: navy+ADs-
FONT-FAMILY: Tahoma+ACIAPg-Electronics
Engineer,+ADw-BR+AD4-Consultant.+ADw-/SPAN+AD4APA-/FONT+AD4APA-/B+AD4APA-/DI
V+AD4- +ADw-DIV dir+AD0-ltr align+AD0-left+AD4APA-B+AD4APA-FONT
face+AD0-Tahoma color+AD0-navy size+AD0-2+AD4APA-SPAN
style+AD0AIg-FONT-WEIGHT: bold+ADs- FONT-SIZE: 10pt+ADs- COLOR: navy+ADs-
FONT-FAMILY:
Tahoma+ACIAPgBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AX
wBfAF8AXwBfADw-BR+AD4APA-/SPAN+AD4APA-/FONT+AD4APA-/B+AD4APA-FONT
face+AD0-Arial color+AD0-navy size+AD0-2+AD4APA-SPAN style+AD0AIg-FONT-SIZE:
10pt+ADs- COLOR: navy+ADs- FONT-FAMILY:
Arial+ACIAPg-Cell:+ACY-nbsp+ADsAJg-nbsp+ADsAJg-nbsp+ADsAJg-nbsp+ADs-
+-972-54-7647107+ADw-BR+AD4-E-Mail: +ADw-A
title+AD0-blocked::mailto:yaronm+AEA-mangodsp.com
href+AD0AIg-mailto:nahshon.mati+AEA-gmail.com+ACIAPg-nahshon.mati+AEA-gmail.
com+ADw-/A+AD4APA-/SPAN+AD4APA-/FONT+AD4APA-/DIV+AD4- +ADw-DIV dir+AD0-ltr
align+AD0-left+AD4APA-FONT face+AD0-Tahoma color+AD0-navy
size+AD0-2+AD4APA-SPAN style+AD0AIg-FONT-SIZE: 10pt+ADs- COLOR: navy+ADs-
FONT-FAMILY: Tahoma+ACIAPgA8-U1:PLACE
u2:st+AD0AIg-on+ACIAPgA8-U1:COUNTRY-REGION u2:st+AD0AIg-on+ACIAPgA8-SPAN
style+AD0AIg-FONT-WEIGHT: bold+ADs- FONT-SIZE: 10pt+ADs- COLOR: navy+ADs-
FONT-FAMILY:
Tahoma+ACIAPgBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AXwBfAF8AX
wBfAF8AXwBfADw-BR+AD4APA-/SPAN+AD4APA-/U1:COUNTRY-REGION+AD4APA-/U1:PLACE+AD
4APA-/SPAN+AD4APA-/FONT+AD4APA-/DIV+AD4APA-/BODY+AD4APA-/HTML+AD4- 

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Adarsha
Sreeramareddy
Sent: Tuesday, November 04, 2008 11:54 AM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on
ML501

Mati,

I tried using PlanAdead 10.1.8, but with no success. Do you have any other
ideas? Should I limit the ICAP frequency to 100 MHz? If so, how do I do it
in EDK?

Should I also specify any ICAP constraint in the UCF file?

Thanks,
Adarsha

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Adarsha
Sreeramareddy
Sent: Monday, November 03, 2008 12:59 PM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on
ML501

I am using the same ICAP and driver versions as in the tutorial. It is
xps_hwicap v1.00.a and driver v2.00.a.

Thanks,
Adarsha

-----Original Message-----
From: owner-partial-reconfig@xxxxxxxxxxxxxx
[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Lu Yi
Sent: Monday, November 03, 2008 3:05 AM
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Problem with partial reconfiguration on
ML501

 I dont know which version of the ICAP and its driver you used, did you use
the same version as in the tutorial?

R.
luyi

> Hi Mati,
>
>
>
> I ran the Math tutorial from the Xilinx website with the current 
> toolset and it works fine. But, when I try incorporating my own PR 
> modules, it gives me the problem. Also, I can load the partial 
> bitstreams successfully through JTAG for my design.
>
>
>
> Thanks,
>
> Adarsha
>
>
>
> From: owner-partial-reconfig@xxxxxxxxxxxxxx
> [mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Mati 
> Nahshon
> Sent: Sunday, November 02, 2008 2:46 PM
> To: partial-reconfig@xxxxxxxxxxxxxx
> Subject: RE: [partial-reconfig] Problem with partial reconfiguration 
> on
> ML501
>
>
>
> I don't know if this is relevant but you should use PlanAhead 10.1.8
>
>
>
> Mati Nahshon
> Electronics Engineer,
> Consultant.
>
> ____________________________
> Cell:     +972-54-7647107
> E-Mail: nahshon.mati@xxxxxxxxx
>
> ____________________________
>
>   _____
>
> From: owner-partial-reconfig@xxxxxxxxxxxxxx
> [mailto:owner-partial-reconfig@xxxxxxxxxxxxxx] On Behalf Of Adarsha 
> Sreeramareddy
> Sent: Sunday, November 02, 2008 10:24 PM
> To: partial-reconfig@xxxxxxxxxxxxxx
> Subject: [partial-reconfig] Problem with partial reconfiguration on
> ML501
>
>
>
> Hello All,
>
> I am trying to design a partial reconfiguration system by loading 
> bitstreams from SysACE to ICAP. My design includes the Microblaze 
> processor and I am using the Virtex 5 (ML501) evaluation kit. I am 
> using ISE 9.2+SP 4 and EDK 9.2+SP 2 along with PlanAhead 10.1.4. I 
> followed the design process from the math example that is provided on 
> the Xilinx web.
>
> I am able to generate the bitstreams and load the full bitstream. But, 
> when I try to partially reconfigure the system, the processor just 
> hangs. I included #define DEBUG 1 and this shows that the bitstream is 
> being read from the CF card and passed onto ICAP. I waited for atleast 
> 30 minutes and it still kept reading the bitstream but nothing 
> happened. My partial bitstreams are around 100KB in size.
>
> One more peculiar problem I see is that when I press the reset button 
> on the board after the processor hangs, nothing seems to happen. The 
> processor does not reset itself.
>
>
>
> Could this be a clocking problem? I place all my DCM modules in the 
> top level design. Is there a particular region on the FPGA, when 
> floorplanning in PlanAhead, where I need to specify the area 
> constraints for the partial reconfiguration modules?
>
>
>
> Or could this be a problem with the HWICAP core?
>
> I would really appreciate it if anyone could help me out as I am on a 
> tight deadline.
>
> Thank you,
> Adarsha
>
>

___________________________
partial-reconfig mailing list
partial-reconfig@xxxxxxxxxxxxxx
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/


___________________________
partial-reconfig mailing list
partial-reconfig@xxxxxxxxxxxxxx
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/


___________________________
partial-reconfig mailing list
partial-reconfig@xxxxxxxxxxxxxx
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/

___________________________
partial-reconfig mailing list
partial-reconfig@xxxxxxxxxxxxxx
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/

References:
- [partial-reconfig] Problem with partial reconfiguration on ML501
  - From: Adarsha Sreeramareddy
- RE: [partial-reconfig] Problem with partial reconfiguration on ML501
  - From: Mati Nahshon
- RE: [partial-reconfig] Problem with partial reconfiguration on ML501
  - From: Adarsha Sreeramareddy
- RE: [partial-reconfig] Problem with partial reconfiguration on ML501
  - From: Lu Yi
- RE: [partial-reconfig] Problem with partial reconfiguration on ML501
  - From: Adarsha Sreeramareddy
- RE: [partial-reconfig] Problem with partial reconfiguration on ML501
  - From: Adarsha Sreeramareddy

Prev by Date: RE: [partial-reconfig] Problem with partial reconfiguration on ML501
Next by Date: RE: [partial-reconfig] Problem with partial reconfiguration on ML501
Previous by thread: RE: [partial-reconfig] Problem with partial reconfiguration on ML501
Index(es):
- Date
- Thread