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Re: [partial-reconfig] SYSACE problems on ML402

To: partial-reconfig@xxxxxxxxxxxxxx
Subject: Re: [partial-reconfig] SYSACE problems on ML402
From: Lu Yi <yilu@xxxxxxxxxxxxxxxxxxxxx>
Date: Wed, 26 Nov 2008 14:46:18 +0100 (CET)
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> Hello,
>
> Another question, dose the sysace_fread() has relation with ICAP?
> I use HWICAP 1.00.b, dirver 1.00c
>

No, sysace_fread() only load bitstream from flash to the buffer you point
to. Checke the codes of XHwIcap_CF2Icap(), you will know how the process
works.

> Thanks for your help.
>
> Best Regards,
> Shih-Shen
>
> 2008/11/26 Lu Yi <yilu@xxxxxxxxxxxxxxxxxxxxx>
>
>> Hello,
>>
>> As far as I know, at least the ICAP module 1.00.b and drive 1.00.c works
>> for V4 board when you use the sysace_fread().
>> check the follwing link and database of Sept.
>>
>> http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2008/09/msg00006.html<http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/archive/2008/09/msg00006.html>
>>
>> regards,
>> luyi
>> > Hello,
>> >
>> > Can I ask a question? Can  you use sysace_fread() to read your
>> bitstream
>> ?
>> > I meet the same problem that sysace_fread() dosen't work. I do not
>> make
>> > sure
>> > that I use ICAP_X0Y1, but I run the ICAP example that show the same
>> output
>> > with yours.
>> > These are the result of the test:
>> >
>> --------------------------------------------------------------------------
>> >  Status: 447
>> > HWICAP Status Register:
>> >    cfgerr_n: 1
>> >    dalign: 1
>> >    rip: 0
>> >    in_abort_n: 1
>> >    Always 1: 1
>> >    Always 1: 1
>> >    Always 1: 1
>> >    Always 1: 1
>> >    Done: 1
>> > -- Reading Device IDCODE through ICAP:
>> > Creating cmd bitstream...
>> > Sending cmd bitstream to ICAP...
>> > Reading from ICAP...
>> > Device IDCODE is: 9321EB40
>> > -- Reading Device IDCODE through ICAP:
>> > Creating cmd bitstream...
>> > Sending cmd bitstream to ICAP...
>> > Reading from ICAP...
>> > Device IDCODE is: 9321EB40
>> >
>> >
>> --------------------------------------------------------------------------
>> > Thanks for the help.
>> >
>> > Best Regards,
>> > Shih-Shen
>> >
>> > 2008/8/28 Paolo Furia <paolo.furia@xxxxxxxxx>
>> >
>> >> I checked the project using the FPGA Editor. The ICAP is correct: I
>> use
>> >> ICAP_X0Y1, accordingly to the constraint you wrote.
>> >> When I do the ICAP test function I obtain two different results. The
>> >> first
>> >> time I do it (after I've programmed the fpga) all "always 1" are '0',
>> >> the
>> >> second time (and others) all "always 1" are '1'. These are the
>> results
>> >> of
>> >> the test:
>> >>
>> >> -- ICAP Base Addr: 0
>> >> ICAP initilized
>> >> -- ICAP Base Addr: 40200000
>> >> -- Reading ICAP Status
>> >>
>> >>  Status: 1
>> >> HWICAP Status Register:
>> >>    cfgerr_n: 0
>> >>    dalign: 0
>> >>    rip: 0
>> >>    in_abort_n: 0
>> >>    Always 1: 0
>> >>    Always 1: 0
>> >>    Always 1: 0
>> >>    Always 1: 0
>> >>    Done: 1
>> >> -- Reading Device IDCODE through ICAP:
>> >> Creating cmd bitstream...
>> >> Sending cmd bitstream to ICAP...
>> >> Reading from ICAP...
>> >> Device IDCODE is: 0
>> >> -- Reading Device IDCODE through ICAP:
>> >> Creating cmd bitstream...
>> >> Sending cmd bitstream to ICAP...
>> >> Reading from ICAP...
>> >> Device IDCODE is: 42088093
>> >>
>> >>
>> >>
>> >> And then (the second time I do it):
>> >>
>> >> -- ICAP Base Addr: 0
>> >> ICAP initilized
>> >> -- ICAP Base Addr: 40200000
>> >> -- Reading ICAP Status
>> >>
>> >>  Status: 447
>> >> HWICAP Status Register:
>> >>    cfgerr_n: 1
>> >>    dalign: 1
>> >>    rip: 0
>> >>    in_abort_n: 1
>> >>    Always 1: 1
>> >>    Always 1: 1
>> >>    Always 1: 1
>> >>    Always 1: 1
>> >>    Done: 1
>> >> -- Reading Device IDCODE through ICAP:
>> >> Creating cmd bitstream...
>> >> Sending cmd bitstream to ICAP...
>> >> Reading from ICAP...
>> >> Device IDCODE is: 42088093
>> >> -- Reading Device IDCODE through ICAP:
>> >> Creating cmd bitstream...
>> >> Sending cmd bitstream to ICAP...
>> >> Reading from ICAP...
>> >> Device IDCODE is: 42088093
>> >>
>> >>
>> >>
>> >> I'm grateful for your help.
>> >>
>> >>
>> >> Regards,
>> >> Paolo Furia
>> >>
>> >>
>> >>
>> >>
>> >>
>> >> 2008/8/27 Lu Yi <yilu@xxxxxxxxxxxxxxxxxxxxx>
>> >>
>> >>> As far as I know, for the Virtex4 FX, the ICAP_X0Y1 should be used,
>> >>> otherwise when you do the ICAP test function, some "always 1"
>> signals
>> >>> will
>> >>> return '0' to you (means it does not work???).
>> >>>
>> >>> So use the FPGA_editor to see if you use the right ICAP.
>> >>> And you can use such constraint in the UCF file to locate your the
>> >>> ICAP:
>> >>>
>> >>> INST
>> >>>
>> >>>
>> "my_system/system_i/opb_hwicap_0/opb_hwicap_0/HWICAP_CTRL_I/GEN_ICAP_VIRTEX4.ICAP_VERTEX4_I"
>> >>> LOC = "ICAP_X0Y1";
>> >>>
>> >>> regards,
>> >>> luyi
>> >>>
>> >>> > How can i know if I'm using the correct ICAP? I put "CONFIG
>> PROHIBIT
>> >>> =
>> >>> > ICAP_X0Y0;" in the UCF file (as in the Xilinx examples). Is it
>> >>> correct?
>> >>> >
>> >>> > Regards,
>> >>> > Paolo Furia
>> >>> >
>> >>> >
>> >>> > 2008/8/27 Lu Yi <yilu@xxxxxxxxxxxxxxxxxxxxx>
>> >>> >
>> >>> >> Could you try the ICAP module 1.00.b, the driver is fine, and
>> make
>> >>> sure
>> >>> >> the ICAP you use is ICAP_X0Y1
>> >>> >>
>> >>> >> regards,
>> >>> >> luyi
>> >>> >>
>> >>> >> > I'm using EDK 9.1.02. ICAP module is opb_hwicap 1.10.a and the
>> >>> driver
>> >>> >> is
>> >>> >> > 1.00.c.
>> >>> >> > I tried that function but it doesn't work.
>> >>> >> >
>> >>> >> > Regards,
>> >>> >> > Paolo Furia
>> >>> >> >
>> >>> >> >
>> >>> >> > 2008/8/27 Lu Yi <yilu@xxxxxxxxxxxxxxxxxxxxx>
>> >>> >> >
>> >>> >> >> Hi, Paolo,
>> >>> >> >>
>> >>> >> >> I am using the EDK8.2.02 to build the main system, my board is
>> >>> ML410,
>> >>> >> >> the
>> >>> >> >> partial reconfiguration by using CF as the bitstream storage
>> is
>> >>> fine.
>> >>> >> I
>> >>> >> >> just use XHwIcap_CF2Icap(&MyIcap, "my.bit") to load the new
>> >>> partial
>> >>> >> >> bitstream, it works fine.
>> >>> >> >>
>> >>> >> >> Which version of your EDK? Which version of your ICAP module
>> and
>> >>> the
>> >>> >> >> ICAP
>> >>> >> >> driver?
>> >>> >> >>
>> >>> >> >> regards,
>> >>> >> >> luyi
>> >>> >> >>
>> >>> >> >> > Hi all,
>> >>> >> >> > I'm working on a dynamically reconfigurable project on ML402
>> >>> >> (virtex-4
>> >>> >> >> > sx35) and, for this, I have to load partial bitstreams from
>> a
>> >>> >> Compact
>> >>> >> >> > Flash. I successfully generated a system.ace file that works
>> >>> fine
>> >>> >> and
>> >>> >> >> > configure my fpga at turn on. The problems come when I try
>> to
>> >>> load
>> >>> >> a
>> >>> >> >> > partial bitstream stored on the CF: it always isn't possible
>> >>> and
>> >>> >> the
>> >>> >> >> > error led turn on.
>> >>> >> >> > I mainly use sysace_fopen and sysace_fread functions (I also
>> >>> tried
>> >>> >> >> using
>> >>> >> >> > directly the function XHwIcap_CF2Icap provided by Xilinx in
>> his
>> >>> >> >> examples);
>> >>> >> >> > only reading 2048 bytes it seems to read something, but not
>> >>> all.
>> >>> >> >> > I tried to open and read an image .bmp, using sysace_fopen
>> and
>> >>> >> >> > sysace_fread, and it works. The problem comes with
>> bitstreams
>> >>> >> >> > (both .bit and .bin).
>> >>> >> >> > I have this problem both in my reconfigurable system and in
>> a
>> >>> >> normal
>> >>> >> >> > system based on MicroBlaze.
>> >>> >> >> >
>> >>> >> >> > Have you any suggestion? Has anyone successfully
>> reconfigured
>> >>> >> virtex-4
>> >>> >> >> > devices using a bitstream stored on a CF? I would be
>> grateful
>> >>> for
>> >>> >> your
>> >>> >> >> > help.
>> >>> >> >> >
>> >>> >> >> >
>> >>> >> >> > Paolo Furia
>> >>> >> >> >
>> >>> >> >>
>> >>> >> >> ___________________________
>> >>> >> >> partial-reconfig mailing list
>> >>> >> >> partial-reconfig@xxxxxxxxxxxxxx
>> >>> >> >> Mailing List Archive :
>> >>> >> >> http://www.itee.uq.edu.au/~listarch/partial-reconfig/<http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> >>> <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> >>> >> <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> >>> >> >>
>> >>> >> >
>> >>> >>
>> >>> >> ___________________________
>> >>> >> partial-reconfig mailing list
>> >>> >> partial-reconfig@xxxxxxxxxxxxxx
>> >>> >> Mailing List Archive :
>> >>> >> http://www.itee.uq.edu.au/~listarch/partial-reconfig/<http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> >>> <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> >>> >>
>> >>> >
>> >>>
>> >>> ___________________________
>> >>> partial-reconfig mailing list
>> >>> partial-reconfig@xxxxxxxxxxxxxx
>> >>> Mailing List Archive :
>> >>> http://www.itee.uq.edu.au/~listarch/partial-reconfig/<http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>> >>>
>> >>
>> >>
>> >
>> >
>> > --
>> > =============
>> > LU SHIH SHEN
>> > +886952136262
>> > =============
>> >
>>
>> ___________________________
>> partial-reconfig mailing list
>> partial-reconfig@xxxxxxxxxxxxxx
>> Mailing List Archive :
>> http://www.itee.uq.edu.au/~listarch/partial-reconfig/<http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
>>
>
>
>
> --
> =============
> LU SHIH SHEN
> +886952136262
> =============
>

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