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On the time I worked on this a while ago
(ISE 8.2) I checked the HW ICAP block using chipscope and realized it was
implemented using 8 bits instead of 32 bits. I have developed my own core that works
with 100Mhz 32 bits and accesses the memory directly without the use of the PPC
to get the maximum performance. Mati
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From: owner- Hello All, I am using Virtex-4 FX60 FPGA and PPC 405 core. The system is running
at 100 MHz. The partial bitstream size is 6,464 bytes. The reconfiguration time
to load the partial bitstream measured by using XTime library is around 5,343,449
cycles. I assume XTime_GetTime is actually getting the clock cycles. This
reconfiguration time is much longer than that I expected. Is it because of the
partial bitstream loaded using software? Maybe there are many bus operation
overhead and CF card access overhead? Is this normal? The software codes are
shown as below. I am using the XHwIcap_CF2Icap provided by Xilinx. Thanks. #include <xtime_l.h> int main (void) { XTime tstamp1,tstamp2; unsigned int config_time; …… XTime_GetTime(&tstamp1); XHwIcap_CF2Icap(&HwIcap, "partial.bit"); XTime_GetTime(&tstamp2); config_time = (unsigned int) (tstamp2-tstamp1); //clock cycles for
reconfiguration xil_printf("\r\nConfig. Time : %ld\r\n", config_time); Best Regards, Jian Huang |