[partial-reconfig] PAR error / bus macro LOC constraints

[Ben Gelb <bgelb@xxxxxxx>]

I am experimenting with some custom bus macros (I created in FPGA 
editor) for a partial reconfiguration design on a Virtex 5. I have 
patterned them after the Virtex4 macros - which use one CLB inside the 
PR region, and one CLB outside. I have used the V5 single-slice macros 
from Xilinx without issue, but really want to use a two-slice macro, so 
that the routing in each PR region can be easily controlled.

My constraints look like this:

INST "tgen" AREA_GROUP = "AG_PRregion1";
AREA_GROUP "AG_PRregion1" RANGE = SLICE_X30Y100:SLICE_X51Y119;
AREA_GROUP "AG_PRregion1" MODE = RECONFIG;
AREA_GROUP "AG_PRregion1" ROUTING = CLOSED;
INST "high4" LOC = SLICE_X28Y100;
INST "low4" LOC = SLICE_X28Y101;
INST "en_macro" LOC = SLICE_X28Y102;

The three "INST" lines are bus macros. The AG range starts at X30, the 
macros are (R-to-L) placed at X28, which makes them straddle the PR 
region boundary (one CLB inside, one CLB outside).

All is well through running map - I get an NCD which has my macros 
placed where I want them, and ratsnest for all of the unrouted nets.

But, when I run it through PAR, I get the following:

ERROR: The component named "en_macro/inside" .
      is owned by more than one Area Group constraint. Each
      component may only be owned by one Area Group constraint.
      Please resolve this constraint conflict by modifying the "SLICEL"
      ranges for the following Area Group constraints:
      Area Group named "AG_PRregion1" owns this comp.
      Area Group named "AG_PRregion1" owns this comp.

For each macro. For some reason its counting the same AG twice? Any idea 
how to fix this?

I should also note that if I run 'drc post_map.ncd' directly, I get the 
same error.

Thanks,
Ben

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