RV: [partial-reconfig] Readback + Frame_ECC in Virtex-4 FPGA

["Iturbe Xabier" <xiturbe@xxxxxxxxxx>]

Dear all,

We are working with Frame_ECC primitive in order to identify the position of a flipped bit in the bitstream. 
In order to do so, we perform a frame readback and we flip a bit writing back the changes.
All this process is performed by means of  a HWICAP(hw:1.10a,sw:1.01a) and a PPC platform. 
According to the "Virtex-4 Configuration User Guide" the identifcator given by the Frame_ECC primitive must be adapted.
 We have done this adaptation in VHDL by means of the following design, where syndrome is the direct output of the primitive:
 
----- 
signal bit_index : std_logic_vector(10 downto 0); 
signal syndrome : std_logic_vector(10 downto 0); 
 
bit_index(10 downto 5) <= syndrome(10 downto 5) - ("01011" & syndrome(10));
bit_index(4 downto 0) <= syndrome(4 downto 0);
------
 
The bit_index value we are obtaining this way is not directly the offset of the flipped bit.
Should the bit_index correspond to the 0-1311 position of the bit flip in the frame data,
or any extra decoding procedure should be done?
      
Thank you for your interest and enjoy your coding ;-) 

Mikel A-a and Xabi


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