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Dear all, Could someone tell us how many frames has
each type of column in a Virtex-4 FPGA? According to XAPP968: CLB type column à 22
frames IO type column à 30
frames DSP type column à21
frames CLK type column à 2
frames MGT type column à 20
frames Block RAM
interconnect column à
20 frames Block
RAM content column à
64 frames We
also know that a Virtex-4 XC4VFX12 device has 4.8 Mbits of configuration
information, which corresponds to the
3600 configuration frames (taken from Virtex-4 Configuration Guide) [3600 fr * 1312
bit/fr = 4723200 configuration bits]. The
problem is that according with the information taken from XAPP968, we
calculate: Each Virtex-4 XC4VFX12 (4 rows) row has 48
CLB columns, 2 IOB columns, 1 CLK column, 1 DSP column and 3 BRAM column.
Therefore: 4 * [(48 * 22) + (2 * 30) + (1 * 2) + (1 * 21)
+ (3 * 84)] = 5564 frames What is wrong in this calculus? Thank you Xabi and Mikel A-a |