[partial-reconfig] Busmacros under modelsim

[Mariusz Grad <Mariusz.Grad@xxxxxxxxxxx>]

Hi,

I think that there is something wrong with simulation busmacros from  
Xilinx (dated 24062008).
I tried to do functional simulation of several designs with these and  
none of them simulated properly, whereas hardware design works.

Does anyone has similar experiences?

Greetings, Mariusz
--
mg



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