Re: [partial-reconfig]

[Heiko Engel <heiko.engel@xxxxxxxxxxxxxxxxxxxxx>]

> According to XAPP968:

I guess you mean XAPP988?

> Each Virtex-4 XC4VFX12 (4 rows) row has 48 CLB columns, 2 IOB columns,
> 1 CLK column, 1 DSP column and 3 BRAM column.

Where did you find this information? I use a FX20 and my slices go from
X0 to X71. With 2 slices per CLB this means I should have 36 CLB rows. I
can't imagine a smaller device has a larger numer of CLB rows. Did you
accidently drop that factor 2? This would give you at least the right
magnitude. Furthermore, according to Virtex4 User Guide there are 8
clock regions in two halves and two rows of the chip which (in my
understanding) should lead to 2 CLK columns?

hope that helps...


regards, heiko
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