[partial-reconfig] Partial Reconfiguration

[Ahmad Salman <asalman@xxxxxxx>]

Dear All,

I have a few questions regarding dynamic reconfiguration:
 
1- In the documentation for the Xhwicap driver (Ver 1.01) I found that
partial bit streams are being transfered from the compact flash to the
main memory (which I think is part of the brams) on system startup then
it is transfered from the memory to the ICAP to do the actual
reconfiguration. If I understand the system right and the above
procedure is what is taking place during partial reconfiguration, my
question is .. do I have access to the bit stream when it is in the main
memory before it is transfered to the ICAP? . If this is true then how
is it possible? .How can I access the .bit file when it is in the memory
and send it to the power pc (or microblaze) and make further changes to
it before it is sent to the ICAP?

2- Can different reconfigurable modules that I predefined in plan ahead
communicate with each other during runtime? if yes then how?

3- Is it possible for the power pc to communicate with a reconfigurable
module directly and not through the icap read/write FIFO?

4- what is the function of the DCMs and the BUFG?

Thanks for your time

Regards,
Ahmad Salman


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