VHDL XSV Board Interface Projects
Project Supervisor: Peter Sutton
Students: James Brennan
These projects are a collection of resources to be used with the XSV board v1.0, produced by XESS Corp. This board contains a Virtex FPGA from Xilinx Inc. and support circuitry for communicating with a wide variety of external devices. This set of resources is designed to provide a set of VHDL entities that act as interfaces to the various capabilities and devices on the XSV board, as well as sample designs that demonstrate the use of the board’s main features. The resources were developed internally by students working for the School of Computer Science and Electrical Engineering in the University of Queensland, Australia. They are made publicly available in the hope that they may be of some help to others who are starting work on similar projects. All VHDL projects were created in Foundation 3.1.
Most of these resources consist of VHDL source code and the accompanying documentation. Below are a list of fully documented projects that were completed, as well as commented source code and the constraint files for each project. Please feel free to contact the authors with any questions or problems, or notify us about any updates that you have done.
|Introduction and Tutorials||HTML||N/A|
|CPLD SVF File Descritions||HTML||Files|
|PC to SRAM Interface||HTML||Files|
|VHDL IP Stack||HTML||Files|
Please note that the HTML versions are best viewed in Internet Explorer, as the Netscape formatting will look ugly and misaligned.
LinksXESS Corporation Board manufacturer
Xilinx FPGA manufacturer
University of Queensland UQ - located in Brisbane, Australia
CSEE School of Computer Science and Electrical Engineering at UQ