The memory wall problem has yet to be solved, though RAMpage seems to be a nice step in that direction. So shouldn't we be planning for the possibility that DRAM could become a slow peripheral?
This project aims to investigate ways of interfacing DRAM to give the best latency, based on the principles of high-end device interfaces from the past.
DRAM Slow Peripheral Projects
- structure of a solution – RAMnet
a good starting point is to try to emulate the design principles of IBM's very successul mainframe disk system - other alternatives?
RAMnet looks like a nice idea, but how else can the problem be addressed?
Other Areas of Research
For now, my home page is the best place to start; there are good links from my Architecture page.
History
Check out my memory history pages.
Philip Machanick philip@itee.uq.edu