Logic synthesis and optimization
Speaker: Elena Dubrova, Royal Institute of Technology, Stockholm, Sweden
When: 2005-11-29 11:00:00
Venue: 78-622
Host: Adam Postula
Abstract:In this talk, I will describe some recent results of my research
group from Royal Institute of Technology (KTH), Stockholm, Sweden,
in the area of logic synthesis. First, I will present the problems
of technology mapping for look-up table based Field Programmable
Gate Arrays, redundancy removal for combinational circuits, and
logic optimization by simulated annealing, and show some solutions
which we offered. Then, I will describe our recent work related to
nano-scale computing.
Biography:Elena Dubrova received the Diploma Engineer degree in Computer
Science from Technical University of Sofia, Bulgaria, in 1993, and
Ph.D. degree in Computer Science from University of Victoria, B.C.,
Canada, in 1997. Currently she is an Associate Professor in
Electronic System Design Lab at the Department of Microelectronics
and Information Technology at Royal Institute of Technology,
Stockholm, Sweden. Her research interests are in logic synthesis,
formal verification and multiple-valued logic.
(http://web.it.kth.se/~elena/)
Type: Embedded Systems Group
Contact:Adam Postula, seminar host (adam@itee.uq.edu.au)
or Guido Governatori (ITEE seminar co-ordinator)
(guido@itee.uq.edu.au)