A Generic Hardware/Software Framework for VPNs Applications using Reconfigurable SoC
Speaker: Adel Ali Alyousef, ITEE
When: 2007-09-17 14:00:00
Venue: 78-420
Host: Prof. Neil Bergmann
Abstract:Nowadays, FPGA device technology gives the ability to the user to
build complex systems through dedicated hardware modules with
specified tasks, and one or more general purpose processors. The
well known feature of the ability of reconfiguring the previous
design in FPGA is a key factor in using reconfigurable computing.
Also due to the increase in the gate count, speed and the reduction
in price, FPGAs became a practical alternative to ASICs in some
applications.
Security protocols utilize cryptography to provide a method for
securing and authenticating the transmission of data over insecure
channels. Such algorithms used in security products like Internet
Protocol Security (IPSec) are complex and can consume a high
processing power. It is for this reason, we employ the hardware
accelerators as coprocessors to reduce the compute time for such
algorithms and to avoid the bottleneck they create. Virtual Private
Networks (VPNs) require high processing demands, especially when
implemented without any hardware acceleration support.
The main goal of this research is to introduce a low cost
sophisticated environment for VPN Gateways. This environment will
include a complete software/hardware co-design framework solution to
be integrated with hardware accelerators blocks for multi algorithms
security protocols. This framework will be implemented with the aid
of the reconfigurable system on chip technology (RSoC).
Biography:Adel A. M. Alyousef completed his BS and MS degrees at King Saud
University in Saudi Arabia, where he also worked as a teaching
assistant before commencing his PhD within the Embedded Systems
group at University of Queensland in 2006.
Type: Ph.D confirmation
Contact:Prof. Neil Bergmann, seminar host (n.bergmann@itee.uq.edu.au)
or Guido Governatori (ITEE seminar co-ordinator)
(guido@itee.uq.edu.au)