Symbolic performance models based on affine arithmetic techniques

Symbolic Circuit Analysis is a technique used to study the behaviour of the circuits using symbols instead of, or in conjunction with, numerical values. The idea of symbolic analysis has been used by the scientists and engineers to study the behaviour of circuits, since the inception of concept of circuits, but due to limited computing facilities, development of this technique was not given much importance. With growing computing and storage capabilities, the research in this field has gained a tremendous momentum and interest among a lot of researchers today. The root difficulty of symbolic analysis is that: the number of product terms in a symbolic expression may increase exponentially with the size of a circuit. For example, for a BiCMOS amplifier that has about 15 nodes and 25 devices, the determinant of the circuit matrix contains more than 10e+11 product terms!! It is essential to keep symbolic analysis expressions as minimal as possible in order for analog designers to gain insight into the circuit behaviour, performance and stability during verification process. The verification process is crucial for many applications in circuit design such as, transistor sizing and optimization, topology selection, sensitivity analysis, behavioural modelling, fault simulation, testability analysis and yield enhancement as pointed out in many research papers. The problem with increase in number of symbolic product terms which require manipulation and evaluation of symbolic analysis will result in CPU time that at best increases linearly with the number of terms. Therefore the CPU computational power will have both time and space complexities that is exponential to the size of the circuit. The analog design flow is a self-validating approach, where the top-down design process starts from a simplified circuit model and the accuracy of these models increases down the path of design process. In other words, the error in the circuit performance models can be known a posteriori. The errors in the models are predominantly not the result of computational procedures adopted but are due to missing data that were neither integrated into the model nor considered during the computational procedure. For example, prior to the layout of a circuit, the influence of the layout parasitics on the circuit performance cannot be predicted, but at the same time are known once the layout is carried out.

My research focuses on development of symbolic techniques to generate symbolic circuit performance models that are capable of self validating themselves. I plan to base these techniques on the self validating numeric such as affine arithmetic. Affine Arithmetic based Symbolic transfer function represents a compact expression, which provides the required insight to the analog designer. In addition, the representation provides the facility to include layout parasitics, which leads to a self-validating performance model.

Interested to know more about this Research Area ? click here to view a pictorial illustration about using Symbolic Analysis in Circuit Design.