Welcome to my home page

[Contact]
Office: Room 78-435
Email: wu@itee.uq.edu.au
Phone: +61 7 3365 8305
School of Information Technology and Electrical Engineering,
The University of Queensland,
Brisbane , Australia

[PhD Topic]
Multiprocessor for reconfigurable System on Chip

[Summary]
In recent years, many applications generally require not only massive data transfer and computation capability, but also complicated/sophisticated system control for real-time processing or user interfaces. It is clear stands that standard uniprocessor architecture will not be able to meet the needed computing power even taking into account the IC technology advances.

Multiprocessor architectures are finding increasing use in fixed system-on-chip designs. We ask the question "What multiprocessor architectures and design methodologies are appropriate for reconfigurable system-on-chip?"

Reconfigurable system-on-chip allows almost infinite variability in the architecture of the systems implemented. Faced with this variability, how can a designer choose the most appropriate system architecture to match their application, requirements and skills?

One of the most cost effective solution is to implement multiple processor cores embedded on specialized chips, such architecture are less expansive to develop and manufacture and consume less power compare to ordinary multi-processor architecture. Chip multi-processor architectures not only offer price-power-performance characteristics, it also provides great scalability and flexibility for embedded applications. However, these benefits will only be achieved if application is optimize in multithreaded and multiprocessing scenarios.