Slides for my confirmation (ITEE RHD/STAFF access only):
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Papers (pending):
A Time-Triggered Hardware Scheduler for RTOS Acceleration in Hard Real-Time Systems
Abstract:
For hard real-time systems, it is essential to execute tasks with a tightly time order. However, for current software-based RTOS, system cannot always meet its hard real-time constraints. This paper reviews hardware acceleration techniques for task scheduling. It introduces a new hardware task management module & scheduler designed specially for embedded hard real-time applications and time-triggered scheduling. This module is designed based on FPGA and targets rSoC systems. It implements novel architecture to accelerate time slice scheduling and time-triggered scheduling.
Keyword: Hard real-time, hardware task management, hardware scheduler, time-triggered, time slicing
Hardware Scheduler:
Objective: use combinational logics (mainly) to create a scheduler to accomplish one-cycle or multi-cycle scheduling. Use a single task state list to control task states. (1 for ready, 0 for stop)
Completed Module:
Bitmap Scheduling: 32 scheduling levels, each level can only hold one task. All the tasks are pre-assigned its priority level- details refer to eCos bitmap scheduling.
Cyclic Scheduling: 32 scheduling levels, scheduler find the next to run task (in the ready tasks) in a cyclic mode.
Both bitmap scheduling and cyclic scheduling use FPGA's carry chain to achieve one-cycle scheduling.
Embedded OS:
osektime compliant eCos: time-triggered task scheduling
If you have interest or comments for my research, please email me.
Thanks.