Yew Tong Yeow

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Associate Professor
Senior Member IEEE
School of Information Technology and Electrical Engineering
The University of Queensland
St Lucia, Queensland
Australia 4072

Phone:0011-61-7-33654442
Fax: 0011-61-7-33654999
Email: yty@itee.uq.edu.au
Link to Home Institution: University of Queensland

Academic Qualifications and Career Path
Qualifications:
BE (1st Class Honours) (Electrical Engineering) University of Canterbury, New Zealand
MSc (Communication Engineering), University of Manchester, England
PhD (Microelectronics), University of Southampton, England

Current Position:
Associate Professor, University of Queensland (1977 - )

Previous Positions Held:
Lecturer, University of Singapore (1976-77)
Post Doctoral Fellow, University of Edinburgh, Scotland (1974-1976)
Lieutenant, Singapore Armed Forces, Singapore (1966-69)

Visiting Positions Held:
Senior Visiting Fellow, Tsinghua University, Beijing, China (2001)
Visiting Scientist, National Institute of Standards and Technology, Gaithersburg, USA (2001)
Senior Fellow, National University of Singapore, Singapore (1997)
Guest Scientist, Siemens Corporate Research Center, Munich, Germany (1990)
Visiting Scientist, IBM TJ Watson Research Center, Yorktown Heights, USA (1986)
Visiting Scholar, University of California, Berkeley, USA (1982)

Research and Teaching Interests
Semiconductor device physics, modelling and technology

Graduated PhD Students and affiliations
M K Alam, Griffith University, Australia

S G Oh, Chung Bok University, South Korea

R Ghodsi, Micron Technology, USA

Z Q Yao (Griffith U, joint supervision), Hua Hong NEC, China

C Y T Chiang, Transcend, Taiwan        

M M Lau, Cypress Semiconductor, USA

C T Hsu, Cypress Semiconductor, USA

P Tanner (Griffith U, joint supervision), Griffith University, Australia

F C J Kong, Micron Technology, USA

Recent Publications

1.     Hong, Y.D, Yeow, Y.T., Chim W. K., Wong, K.M. and J. Kopanski, J.J. Influence of interface traps and surface mobility degradation on scanning capacitance microscopy measurement. IEEE Trans Electron Dev. vol. 51, No. 9, 1496-1503, 2004.

2.     Chim, W.K., Wong, K.M., Yeow, Y.T., Hong, Y.D., Lei, Y., Teo, L.W., Choi, W.K. Monitoring oxide quality using the spread of the dC/dV peak in scanning capacitance microscopy measurements. IEEE Electron Device Letters, vol. 24, No. 10 , 667-670, 2003.

3.     Kong, F.C.J., Yeow, Y.T. and Domyo, H. Characteristics of small-signal capacitances of silicon-on-sapphire MOSFETs. Electron. Letts. 39, No. 4, 407-408 2003.

4.     Chim W.K., Wong K.M., Teo Y.L., Lei Y. and Yeow Y.T. Dopant extraction from scanning capacitance microscopy measurements of p-n junctions using combined inverse modeling and forward simulation. App Phys Letts. 80, No. 25, 4837-4839  2002.

5.     Kong, F.C.J., Yeow, Y.T. and Yao, Z.Q. Extraction of MOSFET threshold voltage, series resistance, effective channel length and inversion layer mobility from small-signal channel conductance measurement. IEEE Trans Electron Dev. vol. 48, No.12, 2870-2874, 2001.

6.     Lau M.M., Chiang C.Y.T., Yeow Y.T. and Yao, Z.Q. A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement. IEEE Trans Electron Dev. vol. 48 No. 8, 1742-1744, 2001.

7.     Hsu C.T., Lau M.M., and Yeow Y.T. Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs. Microelectronics and Reliability. Vol.41 No.2, 201-209, 2001.

8.     Yang, J. and Yeow, Y.T. Modeling study of scanning capacitance microscopy measurement for p-n junction dopant profile extraction. Proceedings of 6 th International Conference on Solid State and Integrated Circuit Technology, Shanghai, China, Oct 2001,1043-1046. Piscataway, New Jersey IEEE. 2001.

9.     Chiang, C.Y.T., Yeow, Y.T. and Ghodsi, R. Inverse modeling of 2-Dimensional MOSFET dopant profile bias capacitance of the source/drain gated diode. IEEE Trans Electron Dev. vol. 47, No. 7, 1385-1392, 2000.

10.  Hsu, C.T., Lau, M.M., Yeow, Y.T. and Yao, Z.Q. Analysis of hot-carrier-induced degradation in mosfet's by gate-to-drain and gate-to-substrate capacitance measurements. Proceedings of 38th Annual International Reliability Physics Symposium, San Jose, April 2000, 98-102. Piscataway, New Jersey IEEE. 2000.

11.  Chiang, C.Y.T., Yeow, Y.T. and Ghodsi, R. Two dimensional mosfet dopant profile by inverse modeling via source/drain-to-substrate capacitance measurement. Proceedings of 3rd International Conference on Modeling and Simulation of Microsystems, San Diego, March 2000, 368-371. Boston, Computational Publications, 2000.

12.  Yip, A., Yeow, Y.T, Samudra, G.S. and Ling, C.H. Modelling of the gated-diode configuration in bulk mosfet's. Proceedings of 3rd International Conference on Modeling and Simulation of Microsystems, San Diego, March 2000, 360-363. Boston, Computational publications, 2000.

13.  Lau, M.M., Chiang, C.Y.T., Yeow, Y.T. and Yao, Z.Q. Measurement of VT and Leff Using MOSFET Gate-Substrate Capacitance. Proceedings of 1999 International Conference on Microelectronic Test Structures, Goteborg, Sweden, March 1999, 152-155. Piscataway, New Jersey IEEE 1999.

14.  Yeow, Y.T. and Ling, C.H. Teaching semiconductor device physics with two-dimensional numerical solver. IEEE Trans Education vol. 42, No. 1, 50-58. 1999.

15.  Chiang, C.Y.T., Hsu, C.T.C., Yeow, Y.T. and Ghodsi, R. Measurement of MOSFET substrate dopant profile via inversion layer-to-substrate capacitance. IEEE Trans Electron Dev. vol. 45, No. 8, 1732-1736. 1998.

16.  Seet, A.W-C and Yeow, Y.T. Teaching of semiconductor device physics with numerical partial differential equations solver, Proceedings of 10 th Australasian Conference on Engineering Education, Gladstone, Qld, Sep 1998. 491-496. Rockhampton, Central Queensland University, 1998.

17.  Phang, C.H., Yeow, Y.T., Barham, R. and Allen, P.J. Measurement of hybrid-p equivalent circuit parameters of bipolar junction transistors in undergraduate laboratories, IEEE Trans Education vol. 40, No. 3, 213-218. 1997.

18.  Ghodsi, R. and Yeow, Y.T. Small-signal gate-to-drain capacitance of MOSFET as a diagnostic-tool for hot-carrier-induced degradation. Microelectronics and Reliability vol. 37, No. 7, 1021-1028. 1997.