Speaker: Ian Clough
Host: Dr Matt D'Souza

Seminar Type:  PhD Thesis Review


Computationally-intensive processing tasks frequently benefit from methods of speedup, be they software or hardware based. While profiling of complex (chains of) tasks can identify suitable candidates for speedup, communication between tasks can often be a bottleneck. Inter-Process Communications (IPC) such as pipes, FIFOs (named pipes) and routers allow a flexible option for optimising these task chains. An Operating System with inbuilt IPC functions can be exploited to achieve this goal, but tradeoffs must be made between simplicity and efficiency. Hardware speedup of tasks can be achieved using FPGAs, which when combined with attached CPUs or peripherals form a System-on-chip, allowing implementation of a mix of Software and Hardware architectures. Whilst this provides speedup opportunities for a software programmer, barriers to hardware implementation have to be considered. Using the Linux OS on a Zedboard FPGA, a moderately complex task has been profiled and split into a chain of communicating tasks implemented as command line functions using different IPC methods, including a software router which allows more flexibility in the connections between tasks. Measurements have been taken of different IPC methods, with and without the software router, to determine overheads, throughput and other metrics. A simple hardware router has also been measured.


Ian Clough received the Advanced Diploma (Electronics) from Southbank TAFE, and B. Eng (Hons) Microelectronics, from Griffith University. He has worked previously for CSIRO (Tropical Animal Sciences, Geomechanics), Griffith University (Environmental Physics, Air Pollution and Noise, Industrial Hygiene), and while at UQ has worked with RBWH/UQCCR (Neonatal Monitoring Project) as well as tutoring many undergraduate subjects. He is currently undertaking an M. Phil in Computer Science, under the supervision of Dr. Matt D’Souza and Professor Neil Bergmann.


78-224; GP-South Room 224